A phase-locked loop (PLL) is widely used in many electrical and computer applications to maintain a fixed phase relationship between an input signal and a reference signal. In general, a phase locked loop is configured to receive an incoming data signal and analyses that data signal to produce an output clock signal that is synchronized to the incoming data signal.
A phase-locked loop typically comprises four main components: a phase frequency detector, a charge pump, a loop filter, an oscillator (VCO) and a frequency divider.
As illustrated in FIG. 1, a phase frequency detector (12) receives a reference clock signal CKref and a feedback clock signal CKfbk and detects the phase and frequency difference therebetween to output UP and DN signals, depending on whether the feedback signal is lagging or leading the reference signal in frequency or phase.
A charge pump (14) receives and transforms the phase difference signals UP and DN into a current Icp that controls the oscillation frequency. The current is dependent on the signal output by the phase frequency detector (12). If charge pump (14) receives an UP signal from the detector (12), indicating that the reference clock signal CKref leads CKfbk, the feedback clock signal, and the current Icp is increased. If charge pump (14) receives a DOWN signal from the detector (12), indicating that the reference signal CKref lags feedback signal CKfbk, and the current Icp is decreased. If no UP or DOWN signal is received, indicating that the clock signals are aligned, charge pump (14) does not adjust the current Icp.
The current then goes to a loop filter (16) and output a voltage. Filter also removes out-of-band, interfering signals. The voltage is then goes to an oscillator (VCO) (18) to control the frequency of the output clock signal. The VCO output signal may be sent back to the phase frequency detector (12) via a feedback loop (20).
When the reference clock CKref leads the feedback clock signal CKfbk, charge pump (12) increases the current Icp to develop a greater voltage Vlf at the output of loop filter (16) which, in turn, causes VCO (18) to increase the output frequency Fout. Conversely, when the reference clock signal CKref lags feedback clock signal CKfbk, charge pump (14) decreases the current Icp to develop a lesser voltage Vlf at the output of loop filter (16) which, in turn, causes VCO (18) to decrease the output frequency Fout. When the reference clock signal CKref and feedback clock signal CKfbk are aligned, voltage Vlf is not adjusted, and the output frequency Fout is kept constant. In this state, PLL is in a “locked” condition.
Phase-locked loops can however suffer from excessive phase jitter at small phase differences. The jitter is caused by a region of low gain, known as the “dead zone”. Dead zone is a region near zero phase error in which the edges of the input and reference signals are so close together that the UP and DOWN inputs are not provided with sufficient opportunity to fully switch and thereby drive the charge pump. As a result, the response to a small phase error is less than it should be, i.e. the response is “deadened”.
This problem has been dealt with, in the past, by inserting delay means into the reset path. However, the drawback of the delay means is the increased noise in the synthesizer loop.
The basic circuit architecture of a phase frequency detector (PFD) is shown in FIG. 2. This conventional PFD has high power consumption and needs large area for a large number of transistors. In many applications, it is desirable and advantageous to integrate all of the components of a PLL on a semiconductor chip. Therefore, a PFD with a small area is needed.
In order to reduce the power consumption, TSPC D-FF has been used in designing PFD. One of the TSPC PFD topologies is ncPFD as shown in FIG. 3. However, the operation of ncPFD of FIG. 3 may have dead zone. Although delays (2 inverters) are inserted at the Fref and Fvco attempting to remove the dead zone, the insertion of the delays or inverters increases the overall power consumption and area.
IEEE symposium on VLSI Circuits Digest of Technical Papers 1994, pp. 129-130, H. Notani et al. discloses a PFD using pre-charged CMOS logic for high frequency operation. It is claimed that the PFD has a minimum detectable phase difference of 40-pico-seconds, and requiting one third the transistors of the conventional circuits. From the diagram as enclosed with the papers, the circuit requires at least 14 transistors. Further, inverters that increase the power consumptions are used in the circuit to reduce dead zone.